The present invention is directed to a device and method which automatically determine whether to interleave pairs of memory banks. More particularly, the present invention maps address bus bits to memory addresses in interleaved and non-interleaved modes which support desired row and column configurations of the memory as stored in a register file.
It is known to interleave memory banks to provide double wide memories so that the memory is used more efficiently. To interleave memory banks in known memory systems, certain types of single in line memory modules (SIMMs) must be placed in the corresponding sockets of a memory motherboard and DIP switches must be set to be indicative of the SIMMs placed in the sockets. Accordingly, these interleaved memory banks require a great deal of user interaction and knowledge. Also, either every memory bank pair in the known memory system must be interleaved or all of the memory banks must operate in a non-interleaved fashion in the known systems. In other words, previous systems do not allow a portion of the memory banks to be interleaved while the remaining portions operate in a non-interleaved fashion. In order to properly operate, each of the SIMMs used must additionally have the same type of row/column configuration, size and speed for interleaving.
One example of a system using interleaved memory is the Macintosh Quadra 800 (Apple Computer, Cupertino, Calif.). In this system, addressing and interleaving signals are all multiplexed together in a single stage. Because the Quadra 800 system has a relatively small number of memory banks (the Quadra 800 has 5 memory bank pairs), a significant delay in producing the end product to the memory does not result. However, as the number of bases in this system increases, the row addresses from the input bus and the interleaving signals are subjected to significantly more logic functions. Therefore, a large delay of the addressing and interleaving signals propagates through to the end product for the memory, and the generation of the interleaving and addressing signals takes more time and slows down the system.
It is therefore desired to provide a system and method for reducing the delays i producing the end product to the memory having a large number of memory banks where portions of the memory banks are interleaved. The present invention is also directed to reducing the amount of user interface necessary to configure a memory system and to increase the efficiency of the memory system by automatically interleaving the memory bank pairs which have the same row and column configurations.